| Top : Enviromental Testing Information : Environmental Testing Seminner : Wafer burn-in system |
| |
|
|
| |
 |
| 5. Outlook for wafer burn-in |
|
|
|
|
|
|
| |
| 5-1 |
Simultaneous burn-in
The wafer burn-in system introduced above can simultaneously burn in 64 die, and so requires 6 scans for an 8-inch wafer. Ideally, simultaneously burning in the entire wafer at once would cut burn-in time dramatically and reduce the cost of testing.
A lot of suggestions have been made for various multi-probe cards to provide simultaneous contact, but at this point reliability and cost prevent them from being practical. I believe that when these problems are solved, we will be able to provide a low-cost system that can simulta-neously burn in the entire wafer.
|
| 5-2
|
Burning in various IC
This system is manufactured primarily for DRAM use. In the future, we plan to offer systems that handle many kinds of burn-in, including many types of memory such as SRAM and flash memory as well as various logic types such as ASIC and MPU. |
| 5-3 |
Test burn-in
Test burn-in can be considered as the next step after dynamic burn-in. There is great demand for a low-cost test burn-in system that can achieve burn-in and function testing rather than high-performance, high-functionality, high-price wafer testers. The key to replacing the wafer tester is the ability to supply a system at low cost. |
|
|
| |
|
|
|
| |
Burn-in at the wafer level is a new method rather than an established technology. However, it can be considered to be an effective approach to handle the supply of KGD and burn-in cost reduction.
The systems offered by ESPEC CORP have been developed for evaluation as wafer burn-in systems. In the future, we would like to receive advice from all quarters so that we can strive for improvements to contribute to the establishment of test technology that achieves wafer burn-in on a practical level.
At any rate, the mutual cooperation and understanding of semiconductor manufacturers and equipment manufacturers is vital to the establishment of test technology using these systems.
|
|
| |
|
|
|
| |
| * |
1. KGD(Known Good Die)
A good bare chip that fulfills specifications. To improve the ratio of good MCM (Multi-Chip Mod-ules), KGD must be mounted. |
| * |
2. Burn-in
Burn-in is generally used to mean exposing parts and equipment to temperatures and voltage that are higher than found in normal use. The purpose is to immediately remove defects caused by the production process. However, with burn-in equipment, semiconductors are subjected to tem-perature and voltage stress during use in the field, accelerating defects. After that, products are tested with testers that measure electrical characteristics to remove defective products.
|
| * |
3. Bare die (bare chip)
A bare chip that only cuts out wafers |
| * |
4. Prober
For mass production lines, fully automatic probers are used. These devices automatically perform the following series of movements with wafers: loading -> auto alignment -> auto probing -> wafer unloading. Temperatures stress can be applied to the wafer using a hot plate. Devices capable of applying 180??qC have been developed to handle the demand for high-temperature burn-in. In December 1997, a prober capable of handling 12-inch wafers was introduced at SEMICON JAPAN. There is hope that if simultaneous burn-in can be achieved, the resulting simplification of the auto alignment function will bring costs down. |
| * |
5. Dicing
Cutting to divide the wafer into individual die. |
| * |
6. Multi-probe card
Inserting multiple probes into a substrate to apply power and test signals to the wafer pad. Wafer probe cards can be divided into two major classifications: needle types and membrane types. The needle types can be further divided based on the shape of the pins into vertical needle types and horizontal needle types. Multi-probe cards are quite expensive, and require maintenance, as they wear out.
|
|
|
| |
|
|
|
| Supplementary explanation of multi-probe cards |
|
|
|
|
|
|
| |
| Here, I would like to introduce the vertical contact multi-probe card (VCPC) offered by Japan Electronic Materials Corporation.
|
| |
| 1. Purpose of VCPC development
|
| 1) |
Handling diverse bonding pad layouts |
| |
| 1. |
Handling diverse numbers of DUT and diverse DUT layouts in simultaneously measuring multiple memory modules.
|
| 2. |
Handling diverse layouts of logic device bonding pads.
|
|
| 2) |
Create probe cards with short probes that can improve high-frequency characteristics |
| |
| 1. |
Create the capacity for wafer tests of devices with actuating frequencies of 200 MHz.
|
|
|
In applying wafer testing to memory devices, emphasis is generally placed on increasing the number of items simultaneously measured, and so development focuses on technology for handling large items and unrestricted DUT layouts. In applying wafer testing to logic devices, attention generally centers on performance of high-speed operation tests, and so development focuses on technology for shortening probes.
|
|
|
| 2.VCPC features
|
| 1) |
Contacts the bonding pad due to stress based on buckling of the vertical probe. |
| 2) |
The needles are located using a specially designed locator guide. |
| 3) |
Makes smaller and neater probe marks than the cantilever type probe card. |
| 4) |
Needle tip is more stable.
|
| 5) |
Can contact the bonding pad with fixed contact pressure (needle pressure), regardless of the number or layout of probes. |
| 6) |
Probe location is less restricted. |
| 7) |
Compatible for use with cantilever probe cards. |
| 8) |
The type with improved electrical characteristics has shorter probes, and is suitable for wafer tests of high-speed devices. |
|
|
| |
| 2.VCPC specification
|
| |
Table 2 gives VCPC specifications, and Photo 3 shows a VCPC. |
|
|
| |
|
Table 2 VCPC (Vertical Contact Probe Card) specifications
|
|
Photo 3 VCPC |
| |
|
1
|
Needle position precision |
±10μm |
|
2
|
Needle tip height dispersion |
20μm?OE`?n? |
|
3
|
Minimum pitch |
150μm |
|
4
|
Probe materials |
Tungsten
Tungsten impregnated with Rhenium |
|
5
|
Probe diameter |
80μm |
|
6
|
Total probe length
(from substrate connection to needle tip) |
15 ~ 20mm |
|
7
|
Tip diameter |
20 ~ 30μm |
|
8
|
Tip length |
400 ~ 500μm |
|
9
|
Needle tip shape |
Ball shaped (point contact)
Flat (surface contact) |
|
10
|
Slip (with 75 mm drive) |
0 ~ 10μm |
|
11
|
Operational temperature range |
20 ~ 100?? |
|
12
|
Maximum needle region |
120 x 120mm angular |
|
13
|
Maximum number of probes |
2000 |
|
14
|
Needle pressure(with 50μm drive) |
10 ~ 20g |
|
15
|
Contact resistance |
Maximum 1Ω |
|
16
|
Maximum current |
250mA |
|
17
|
Maximum voltage |
50V |
|
18
|
Capacity(substrate - probe) |
20pF(standard value) |
|
19
|
Capacity(probe only) |
3pF(standard value) |
|
20
|
Inductance(substrate - probe) |
65nH(standard value) |
|
21
|
Inductance(probe only) |
10nH(standard value) |
|
|
|
 |
|
|
| |
|
|
|
| |
| 1) |
Kenji Numata, "KGD foundamenal of wefer-level", Electronic Parts and Materials, (1995.4) |
| 2) |
Yuuichi Abe, "Wefer-prober", Electronic Parts and Materials an independent volume, (1996) |
| 3) |
Electronic Journal?Cp.21(1995.11)
|
| 4) |
Nikkei Microdevices, p.101, (1996.9)
|
| 5) |
Isao Yano, "System of Wefer burn-in", Electronic Parts and Materials an independent volume, (1996) |
| 6) |
Terminological Dictionary of Semiconductor Equipment 4th Edition, Semiconductor Equipment Association of Japan
|
|
|
| |
|
|
|
