 |
 |
|
|
 |
|
 |
 |
|
|
|
Isao Yano*
Wafer burn-in is attracting attention as the most effective measure for reducing burn-in*1 cost and obtaining KGD*2 (Known Good Die) in semiconductor production. In this article I would like to discuss the merits and major themes of wafer burn-in, and present the wafer burn-in system developed by ESPEC CORP. |
|
 |
 |
|
|
 |
|
|
|
| Nowadays, burn-in
is crucial to semiconductor production, and
to DRAM production in particular. However,
as memory capacity increases, more time is
required for burning in, and efforts are under
way to achieve a means of reducing test costs.
Entering the multimedia era has created a
need for products able to process large quantities
of data at high speed, leading to increasing
demand for bare die*3 mounting such as the
MCM (Multi-Chip Module) and the COB (Chip
on Board). Because of this, the supply of
bare die with verified reliability known as
KGD (Known Good Die) has become vital. KGD
technology is already in use in the pre-existing
Die Level method, but that method requires
a special socket for testing and needs to
have cost problems resolved. In answer to
the anticipation for a means of solving these
problems, I would like to present the Wafer
Burn-in, a burn-in done at the wafer level. |
|
|
|
|
| 2. The merits of Wafer Burn-in |
|
|
|
|
|
|
Burn-in at the
wafer level has a variety of merits besides
assuring KGD. At this point, I would like
to present four merits of wafer burn-in for
DRAM.
| ( 1 ) |
Reduced burn-in time
For increasingly large-capacity DRAM,
a major theme for burn-in has become
reducing burn-in time and lowering the
cost of testing.
Currently, burn-in time is almost exclusively
for assuring cell reliability. Two problems
stemming from this increased capacity
are: (1) the increase in the length
of the cell refresh cycle brings a corresponding
decrease in the efficiency of applying
stress, and (2) there is a limit to
the pressure rise of word line potential
when applying stress voltage that makes
adequate voltage acceleration for peripheral
circuits impossible with PKG (package)
burn-in.
With wafer burn-in, special burn-in
circuits are built into the wafer to
resolve these problems, and burn-in
time can be reduced by efficiently driving
these special circuits. |
| ( 2 ) |
Appropriate for all
types of DRAM
Currently new DRAM such as SDRAM and
MDRAM are continually being developed
that are difficult to access with PKG
burn-in. While these types of DRAM have
different access methods, they retain
the same cell structure.
When the burn-in is done at the wafer
level, direct contact can be made with
the special burn-in pad. In this way,
regardless of the type of DRAM used,
effective stress can easily be applied
to the memory cell. |
| ( 3 ) |
Applying heat stress
more accurately
The hot plate of a prober*4 can apply
heat stress directly to the wafer. This
makes it possible to reduce heating
up time and to accurately control junction
temperature. |
| ( 4 ) |
Improving yields
Wafer burn-in is used in IC production
processes such as shown in Fig.1. Based
on the defect report from the wafer
tester following burn-in, it may possible
to improve yields by such measures as
replacing the redundancy memory of the
defective cell. In addition, the feedback
this report provides to the previous
process can lead to improved reliability
by initiating immediate improvement
of the production process. |
|
|
|
Fig. 1
IC production process
|
|
|
|
|
| |
|
|
| 3. Wafer burn-in problems |
|
|
|
|
|
|
| The merits of wafer burn-in are
made available by solving the following two problems.
|
|
3-1
Achieving effective, economical burn-in circuits
Special burn-in circuits inside the wafer
are required to apply efficient stress to
the cell and to apply effective stress voltage
to peripheral circuits. These circuits must
make as little impact as possible with regard
to die size and must be able to apply effective
stress within a short time. Adding burn-in
circuits without making special considerations
can increase the cell surface area as much
as five percent. The key to successful wafer
burn-in is the ability to economically achieve
effective burn-in circuits.
Proposals concerning these burn-in circuits
are in the reference document 1) , and so
I will present some reference circuits in
Fig. 2.
| ( 1 ) |
Applying
DC stress to memory cells
Transistors for applying stress are
added to each word line and stress is
directly applied to the word line from
a special pad. In this way, stress can
be applied without being affected by
the refresh cycle. |
| ( 2 ) |
Applying stress voltage
to peripheral circuits
When dynamic stress voltage is applied
to peripheral circuits, word line pressuring
up is stopped, and it becomes possible
to apply high voltage stress to the
peripheral circuits. |
| ( 3 ) |
Automatic dynamic motion
Designing circuits that automatically
provide dynamic motion at peripheral
circuits can make efficient burn-in
possible. |
This data is somewhat old, but it is reported
that when giving these circuits to 4M DRAM,
efficient burn-in can be achieved with DC
stress applied for two minutes to the word
line and dynamic stress applied for 3 minutes
to the peripheral circuits.
3-2 Multi-probe card*6 reliability
and economical operation
To reduce burn-in time, the ability to apply
stress simultaneously to a number of die is
vital. To do so, many have called for putting
a large number of pins on the probe card.
With a large number of pins, the key is how
to achieve reliable and economical operation
in spite of such problems as pin life, pin
maintenance, getting the pins and the pads
aligned, and pin misalignment caused by thermal
expansion of the pins during heat stress.
The vertical needle type and the membrane
type are currently receiving a lot of attention
for handling large numbers of pins, and there
is great anticipation that these technologies
will be developed soon. The membrane type
has received a lot of attention as a means
of handling larger numbers of pins and higher
speeds, but at present the vertical needle
type is more practical. The vertical needle
VCPC developed by the Japan Electronic Materials
Corporation makes grid arrangement possible,
and the pins are shorter with less dispersion
in length. ESPEC CORP recommends this VCPC.
|
|
|
Fig.
2 Burn-in circuits
|
|
 |
|
|
|
|
| 4. The true state of
wafer burn-in systems |
|
|
|
|
|
|
|
|
|
Table
1 Wafer burn-in system specifications
(WBD-02)
|
|
|
|
| (1)
Prober |
UF200 (Tokyo
Seimitsu Co.
Ltd.) [Or, Tokyo
Electron Limited
(p-8).] |
| (2)
Handlingcapacity
|
64 die simultaneous
probing (maximum) |
| (3)
Mask functions
for each die |
Fail indication
die interrupts
power and clock.
|
| (4)
Test temperature
range |
50
to 130°C |
|
|
Die
power
|
| (1)
Number of
power sources |
1 |
| (2)
Voltage range
|
2 to 7 V |
|
(3)
Power capacity
|
150 mA/die |
| (4)
Protection
functions
|
OVP,
OCP detection |
|
|
Timing
occurrence
|
| (1)
Cycle Time |
100 nS to 10µS |
| (2)
Resolution |
10 nS |
| (3)
Number of clocks
|
8 |
| (4)
Protection functions
|
15 |
|
|
Clock
driver
|
| (1)
Number of clocks |
8 ch/die |
| (2)
VIH |
2 to 7 V, can
be set for each
clock |
| (3)
VIL |
0 to 4 V, -2
to 0 V (CLK6),
can be set for
each clock |
| (4)
Tr/Tf |
30nS/5V/50pF,
200µS/5V/2µF |
| (5)
Clock monitoring
functions |
Window
comparater |
| (6)
Contact check
functions |
Handles
full clock |
|
|
Measuring
functions
|
| (1)
V1 Supply amperage |
Measurement
range, 0 to
250 mA |
| (2)
Contact check
pressure |
Measurement
range, 0 to
-2 V |
|
|
Dimensions
|
| (1)
Size (mm) |
2344 (W) x 1416
(D) x 1834 (H) |
| (2)
Weight |
Approx. 950
kg |
|
|
|
|
|
|
Fig.
3 System block diagram
|
|
|
|
|
|
|
|
|
