The Flash Memory Endurance Cycling System is a monitored burn-in system that evaluates flash memory, FeRAM, and other nonvolatile memory.
With flash memory, it is possible for the tester to transfer test functions using the pattern generation function that enables generation of complex algorithms, bad block management function, and Vth distribution measurement function. This system was designed for expandability and flexibility to accommodate nonvolatile memory tests developed in the future, and it provides testing and inspection from nonvolatile memory R&D to mass production.
- Applicable devices
- Flash memory is rewritable and is a nonvolatile semiconductor memory that does not erase the data even if the power supply is turned off. While there are NAND and NOR flash memory, the demand for NAND flash memory has suddenly grown with the popularity of portable music players. (Pictured: NAND flash memory using 43 nm process technology, Toshiba Corporation, 16/32 GB)
- High capacity and high speed processing of flash memory erase/write cycle test
- Supports block management of NAND flash memory
- Equipped with flexible pattern generator (ALPG)
- Uses a multiple chamber system for easy temperature testing and evaluation with multiple standards
- System block diagram
RBM-LCT-PST01 Chamber Variation High/Low Temp.
High Temp. Chamber×1
High/Low Temp.Chamber ×2
Chamber less Operating temperature -55°C to 150°C High Temp. Chamber
+70°C to 150°C
-55°C to 150°C
Slot 12 12 1 Zone 12 12 1 System
Cycle time / Resolution 100nS to 0.6mS / 10nS Timing number 30 Clock frequency 16 Strobe 2 Clock resolution 10nS DUT Power PS1、PS2 0.8V to 8.0V / 10A PS3 - PS5 1V to 15V / 6A PS6 -1V to -15V / 6A Output accuracy ±（2%+50mV）